Research
Fault-tolerant Network-on-Chip architecture
I am a member of the project as a Ph.D. student at ASL from 2014 to 2017. We developed a comprehensive solution to tackle the reliability of on-chip interconnect. We have developed tolerance method for the permanent (hard), transient (soft), and TSV defect. Selected publications:
Khanh N. Dang, Akram Ben Ahmed, Yuichi Okuyama, Abderazek Ben Abdallah, “Scalable design methodology and online algorithm for TSV-cluster defects recovery in highly reliable 3D-NoC systems”, IEEE Transactions on Emerging Topics in Computing (TETC), IEEE, (in press). [link].
Khanh N. Dang, Akram Ben Ahmed, Xuan-Tu Tran, Yuichi Okuyama, Abderazek Ben Abdallah, “A Comprehensive Reliability Assessment of Fault-Resilient Network-on-Chip Using Analytical Model”, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), IEEE, Volume 25, Issue 11, pp 3099-3112, 2017. [link].
Khanh N. Dang, Michael Meyer, Yuichi Okuyama, Abderazek Ben Abdallah, “A Low-overhead Soft-Hard Fault Tolerant Architecture, Design and Management Scheme for Reliable High-performance Many-core 3D-NoC Systems”, Journal of Supercomputing, Springer, Volume 73, Issue 6, pp 2705–2729, 2017. [link]. Patent
A. Ben Abdallah, Khanh N. Dang, Masayuki Hisada, “A TSV fault-tolerant router system for 3D-Networks-on-Chip”, 特願 2017-218953, Japan patent (under review).
Caption: The layout of a layer 2x2 in OASIS project: NANDGATE 45nm, NCSU FreePDK TSV. The TSV size, pitch and Keep-out Zone are 4.06umx4:06um,
10um, and 15um, respectively. TSV area is shared between the neighboring routers for tolerating TSV defect. The project won Second Prize (the 2nd best) of Vietnamese Talents Award 2015.